PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace. According to the “PCI ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

This collaboration highlights GUC's commitment to deliver comprehensive and innovative design solutions, enabling customers ...

This funding will support the continued development and demonstration of Strategic Radiation Hardened (SRH) high reliability ...

A jury in Wilmington, Delaware, has found that Qualcomm’s latest AI-PC processors – based on the ARM instruction set – are ...

TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and ...

VeriSilicon (688521.SH) today announced the launch of its latest Vitality architecture Graphics Processing Unit (GPU) IP ...

As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. System and chip designers ...

As part of its transition back to a pure-play IP company, Ceva officially launched its NeuPro-Nano earlier this year. The ...

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ... Rambus ...

The jury is out on the fourth day of the Arm vs Qualcomm lawsuit with the attorneys for both sides completing their closing ...