Design-Reuse3y
PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs
Both IP core come with x4 physical lane width and support for dual-port PLL with LC tanks enabling parallel interface of 16/32- bit (Gen4/5) The PCIe 5.0 Serdes PHY IP core is compliant with PCIe 5.0 ...
Design-Reuse17y
Altera's FPGAs Are First to Demonstrate Support for PCI Express 2.0
The PLDA XpressGXII prototyping board includes PLDA’s PCI Express intellectual property (IP) core, IP configuration software, and the corresponding test-bench and reference designs for x1, x2, x4 and ...